According to our best knowledge, there are only a few examples available in the open literature concerning the hardware realisation of DTs. Typically, DTs are implemented in software. DTs are rooted tree structures, with leaves representing classifications and nodes representing tests of features that lead to those classifications. ĭTs represent well known predictive models, originally proposed by Breiman et al. There are many different predictive models (classifiers) in machine learning, including artificial neural networks (ANN), decision trees (DTs) and recently introduced support vector machines (SVMs). Experimental results obtained on 23 data sets of standard UCI machine learning repository database suggest that the proposed architecture based on the sequence of UNs requires on average 56% less hardware resources compared with previously proposed architectures, having the same throughput. Developed IP cores can be easily customised in order to fit a wide variety of application requirements, fulfilling their role as general purpose building blocks for SoC designs.

Proposed IP cores are suitable for implementation in both field programmable gate arrays and application specific integrated circuits. Abstract: Several softintellectual property (IP) core implementations of decision trees (axis-parallel, oblique and nonlinear) based on the concept of universal node (UN) and sequence of UNs are presented.

Iet computers & digital techniques